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CM3196 2A Sink/Source DDR-I, -II Bus Termination Regulator
Features
* * * * * * * * Ideal for DDR-I, -II VTT applications Sinks and sources 2A for DDR-I, 0.6A for DDR-II Shutdown input to support ACPI states Operates down to 1.5V input voltage Integrated power MOSFETs Overcurrent protection Over temperature protection Excellent accuracy VTT = VREF 30mV VTT = VDDQ/2 2% 8-pin SOIC or PSOP package Lead-free versions available
Product Description
The CM3196 is a sinking and sourcing regulator specifically designed for DDR-I, -II VTT bus termination. The output voltage accurately tracks VDDQ/2. For DDR-I it can source and sink current up to 2A with a load regulation of 0.5%. This current adequately serves both single and dual channel DDR-I memory systems. For power conscious notebook applications, the CM3196 also operates from a VDDQ of 1.5V or 1.8V with less current drive. For DDR-II applications, the CM3196 provides up to 0.6A at 0.9V to drive the memory controller VTT. For boards which support Suspend to RAM (STR) functionality, the CM3196 provides a Shutdown (SD) pin. When SD is set low, VTT will be in tri-state mode, causing the output to go high impedance. In this mode, CM3196 power is saved by significantly reducing the quiescent current. VREF voltage remains VDDQ/2. The CM3196 provides overcurrent and over temperature protection. These features protect the chip from excessive heating due to high current and high temperature. The CM3196 is housed in an 8-pin SOIC or PSOP package and is available with optional lead-free finishing.
* *
Applications
* * * DDR-I, -II memory termination Active termination buses Graphics card memory termination
Simplified Electrical Schematic
AVIN VDDQ PVIN
SD
Over Temp Over Current Reference
50K
Driver
VREF
OUT
IN
VTT
50K
Buffer
VSENSE
GND
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
CM3196
PACKAGE / PINOUT DIAGRAM
TOP VIEW
GND SD VSENSE V REF
1 2 3 4 8 7 6 5
TOP VIEW
VTT PVIN AVIN VDDQ GND SD VSENSE VREF
1 2 3 4 8 7
GND
6 5
VTT PV IN AV IN VDDQ
8-lead SOIC
Note: This drawing is not to scale.
8-lead PSOP
PIN DESCRIPTIONS
LEAD(S) 1 2 3 4 5 6 7 8 NAME GND SD VSENSE VREF VDDQ AVIN PVIN VTT DESCRIPTION Ground Shutdown input, active low Feedback from VTT input Reference output, VDDQ/2 VDDQ input Analog circuit power input Power transistor input Output
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Ordering Part Pins 8 8 Package SOIC-8 PSOP-8 Number1 CM3196-12SN CM3196-12SB Part Marking CM3196-12SN CM3196-12SB Lead-free Finish Ordering Part Number1 CM3196-12SM CM3196-12SH Part Marking CM3196-12SM CM3196-12SH
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
04/22/04
CM3196
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER AVIN Operating Supply Voltage VDDQ Input Voltage Pin Voltages VTT Output Any other pins Storage Temperature Range Operating Temperature Range Ambient Junction Power Dissipation (See note 1) RATING 7 7 7 7 -40 to +150 -40 to +85 -40 to +150 Internally Limited UNITS V V V V C C C W
Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in an 8-pin SOIC package must be derated at JA = 151C/W and the 8-pin PSOP must be derated at JA = 43C/W.
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
CM3196
Specifications (cont'd)
DDR-I Features
STANDARD OPERATING CONDITIONS
PARAMETER VDDQ AVIN PVIN Ambient Operating Temperature CVOUT VALUE 2.5 2.5 2.5 -40 to +85 220 +20% UNITS V V V C F
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL VIN PARAMETER Input Voltage Range PVIN pin AVIN pin AVIN Quiescent Current AVIN Quiescent Current in Shut Down VTT Output Voltage PVIN = 2.5V PVIN = 1.8V PVIN = 1.5V Output Reference Voltage Output Offset from V REF VREF Output Impedance VDDQ Input Impedance VTT Current Limit Shutdown Logic Logic "1" Level Logic "0" Level Shutdown Temperature Thermal Hysteresis 1.5 0.4 150 30 IREF = -5A to 5A ITT = 0A VSD = logic "0" CONDITIONS MIN 2.2 2.2 TYP 2.5 2.5 450 115 MAX AVIN 5.5 UNITS V V A A
ICC ICCSD VTT
ILOAD = 0 to 2A or ILOAD = -2A to 0A ILOAD = 0 to 0.75A or ILOAD = -0.75A to 0A ILOAD = 0 to 0.3A or ILOAD = -0.3A to 0A
1.225 1.225 1.225 1.225 -30
1.250 1.250 1.250 1.250
1.275 1.275 1.275 1.275 30
V V V V mV k k A V V C C
VREF VOSVTT ZREF ZVDDQ ILIM VSD
VDDQ = 2.5V, IREF = 0A
5 100 2.5
TDISABLE THYST
Note 1: Operating characteristics are over Standard Operating Conditions unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
04/22/04
CM3196
Specifications (cont'd)
DDR-II Features
STANDARD OPERATING CONDITIONS
PARAMETER VDDQ AVIN PVIN Ambient Operating Temperature CVOUT VALUE 1.8 3.3 1.8 -40 to +85 220 +20% UNITS V V V C F
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL VIN PARAMETER Input Voltage Range PVIN pin AVIN pin AVIN Quiescent Current AVIN Quiescent Current in Shut Down VTT Output Voltage PVIN = 1.8V PVIN = 1.5V AVIN > 2.2V, PVIN > 2.2V Output Reference Voltage Output Offset from V REF VREF Output Impedance VDDQ Input Impedance VTT Current Limit Shutdown Logic Logic "1" Level Logic "0" Level Shutdown Temperature Thermal Hysteresis 1.5 0.4 150 30 IREF = -5A to 5A ITT = 0A VSD = logic "0" CONDITIONS MIN 1.5 2.2 TYP 1.8 3.3 450 115 MAX AVIN 5.5 UNITS V V A A
ICC ICCSD VTT
ILOAD = 0 to 0.6A or ILOAD = -0.6A to 0A ILOAD = 0 to 0.3A or ILOAD = -0.3A to 0A ILOAD = 0 to 1.2A or ILOAD = -1.2A to 0A
0.882 0.882 0.882 0.882 -30
0.9 0.9 0.9 0.9
0.918 0.918 0.918 0.918 30
V V V V mV k k A V V C C
VREF VOSVTT ZREF ZVDDQ ILIM VSD
VDDQ = 1.8V, IREF = 0A
5 100 2.5
TDISABLE THYST
Note 1: Operating characteristics are over Standard Operating Conditions unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
CM3196
Performance Information
Typical DC Characteristics (nominal conditions unless otherwise specified)
Figure 1. Output Voltage with Supply (VDDQ = 2.5V)
Figure 3. Load Regulation (Sink)
Figure 2. Reference Voltage with Supply (VDDQ = 2.5V)
Figure 4. Load Regulation (Source)
(c) 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
04/22/04
CM3196
Performance Information (cont'd)
Typical DC Characteristics (nominal conditions unless otherwise specified)
Figure 5. Over Current Limit (Sink)
Figure 7. Over Current Limit (Source)
Figure 6. Supply Current with Supply Voltage
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
7
CM3196
Performance Information (cont'd)
Typical Transient Characteristics (nominal conditions unless otherwise specified)
Figure 8. Load Transient (0A to 2.0A Sink)
Figure 9. Line Transient (0A to 2.0A Source)
(c) 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
04/22/04
CM3196
Performance Information (cont'd)
Typical Thermal Characteristics The overall junction to ambient thermal resistance (JA) for device power dissipation (PD) consists primarily of two paths in series. The first path is junction to case ( JC) which is defined by the package style, and the second path is case to ambient (CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TA + PD ( JC) + PD (CA) = TA + PD (JA) When a CM3196-12SN (SOIC) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting JA is 151C/W. Based on the over temperature limit of 150C with an ambient of 85C, the available power of this package will be: PD = (150C -85C) / 151C/W = 0.43W For the CM3196-12SB (PSOP), JA is 40C/W and the available power for this package will be: PD = (150C -85C) / 40C/W = 1.625W DDR Memory Application Since the output voltage is 1.25V, and the device can either source current from VDD or sink current to Ground, the power dissipated in the device at any time is 1.25V times the current load. This means the maximum average RMS current (in either direction) is 0.344A for CM3196-12SN and 1.3A for CM3196-12SB. The maximum instantaneous current is specified at 2A, so this condition should not be exceeded 17% and 65% of the time for CM3196-12SN and CM3196-12SB, respectively. It is highly unlikely in the use of DDR memory that this would occur, because it means the DDR memory outputs are either all high or all low for 17% (SOIC) and 65% (PSOP) of the time. If the ambient temperature is 40C instead of 85C, which is typically the maximum in most DDR memory applications, the power dissipated (PD) can be 0.73W for CM3196-12SN and 2.75W for CM3196-12SB. So the maximum average RMS current increases from 0.42A to 0.58A for CM3196-12SN and maximum
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
instantaneous current of 2A should not be exceeded 29% of the time. For CM3196-12SB, the maximum RMS current increases from 1.3A to 2.2A. Thus, the maximum continuous current can be 2A all the time.
Figure 10. Duty Cycle vs. Ambient Temperature (ILOAD = 2A)
Figure 11. Duty Cycle vs. Output Current (Temp=70C)
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
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CM3196
Performance Information (cont'd)
Typical Thermal Characteristics (cont'd) The theoretical calculations of these relationships show the safe operating area of the CM3196 in the SOIC package. Thermal characteristics were measured using a double-sided board with two square inches of copper area connected to the GND pins for "heat spreading." Measurements showing performance up to a junction temperature of 150C were performed under light load conditions (5mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. Figure 13. Output Voltage vs. Ambient Temperature (ILOAD=5mA)
Figure 12. Reference Voltage vs. Temperature Figure 14. Quiescent Current vs. Temperature
(c) 2004 California Micro Devices Corp. All rights reserved.
10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
04/22/04
CM3196
Application Information
PCB Layout Considerations The CM3196-12SB has a heat spreader attached to the underneath of the PSOP-8 package in order for heat to be transferred easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq. in. of copper adjacent to the vias. It also helps if the chip is positioned away from the edge of the PCB, and not near other heat dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will properly couple the CM3196 package to maintain an ambient junction temperature (JA) of around 40C/W.
Figure 15. Recommended Heat Sink PCB Layout
SD VDDQ AVIN PVIN
CAVIN 47F
SD VDDQ AVIN PVIN
CPVIN 47F
VREF VSENSE VTT
CVREF 0.1F
VREF
GND
VTT
CVout 220F
Figure 16. Typical Application Circuit
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
11
CM3196
Mechanical Details
The CM3196 is available in an 8-lead SOIC and PSOP package. SOIC-8 Mechanical Specifications Dimensions for CM3196 devices packaged in 8-pin SOIC packages are presented below. For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Information document.
H
Pin 1 Marking 8
Mechanical Package Diagrams
TOP VIEW
D
7 6 5
E
PACKAGE DIMENSIONS
Package Leads Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Max 1.75 0.25 0.51 0.25 5.00 4.19 6.20 1.27 Min 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.016 SOIC 8 Inches Max 0.069 0.010 0.020 0.010 0.197 0.165
END VIEW SEATING PLANE SIDE VIEW 1 2 3 4
A A1 B e
1.27 BSC
0.050 BSC 0.244 0.050
L C
100 pieces* 2500 pieces Controlling dimension: inches
Package Dimensions for SOIC-8
* This is an approximate number which may vary.
(c) 2004 California Micro Devices Corp. All rights reserved.
12 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
04/22/04
CM3196
Mechanical Details
PSOP-8 Mechanical Specifications Dimensions for CM3196 devices packaged in 8-pin PSOP packages with an intagrated heatslug are presented below. For complete information on the PSOP-8 package, see the California Micro Devices PSOP-8 Package Information document. Mechanical Package Diagrams
TOP VIEW
D
8 7 6 5
PACKAGE DIMENSIONS
Package Leads Dimensions A A1 B C D E e H L x** y** # per tube # per tape and reel Millimeters Min 1.30 0.03 0.33 0.18 4.83 3.81 1.02 5.79 0.41 3.56 2.29 Max 1.62 0.10 0.51 0.25 5.00 3.99 1.52 6.20 1.27 4.06 2.79 Min 0.051 0.001 0.013 0.007 0.190 0.150 0.040 0.228 0.016 0.130 0.090 PSOP-8 8 Inches Max 0.064 0.004 0.020 0.010 0.197 0.157 0.050 0.244 0.050 0.150 0.110
H
Pin 1 Marking
E
1
2
3
4
BOTTOM VIEW
D
1 2 3 4 Heat Slug
x Hy E
x/2 y/2
8
7
6
5
100 pieces* 2500 pieces Controlling dimension: inches
SIDE VIEW
A
SEATING PLANE
A1 B e
END VIEW
* This is an approximate number which may vary.
** Centered on package centerline.
C
L
Package Dimensions for PSOP-8
(c) 2004 California Micro Devices Corp. All rights reserved. 04/22/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
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